C8051F326 Datasheet, PDF (51/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
6.3.2. External Interrupts
The /INT0 active low external interrupt source is mapped to P0.0 (or P0.2 when TMOD.3 is logic 1) and
can be configured as edge or level sensitive. The IT0 bit (TCON.0, see Figure 14.1 on Page 133) selects
level or edge sensitive. When global port I/O inputs are enabled, /INT0 will monitor the voltage at the input
pin. The CPU will vector to the /INT0 interrupt service routine once a falling edge or low signal is detected.
The /INT1 interrupt source provides an interrupt on two events, based on the logic level of GATE1
(TMOD.7). If GATE1 is set to logic 1, an interrupt is generated every two Low Frequency Internal Oscillator
clock cycles. This allows the CPU to vector to the /INT1 interrupt service routine at a rate of 40kHz. If
GATE1 is set to logic 0, an interrupt is generated when the internal oscillator resumes from a suspended
state.
The pending flags for the /INT0 and /INT1 interrupts are set upon reset. If the /INT0 or /INT1 interrupt is
used, the respective flag should be cleared before enabling the interrupts to prevent an accidental inter-
rupt. The pending flags are for the /INT0 and /INT1 interrupt are in the TCON register.
6.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 6.4.
6.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
The CPU is stalled during Flash write/erase operations. Interrupt service latency will be increased for inter-
rupts occurring while the CPU is stalled. The latency for these situations will be determined by the standard
interrupt service procedure (as described above) and the amount of time the CPU is stalled.
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