C8051F326 Datasheet, PDF (110/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
12.11. Configuring Endpoint1
Endpoint1 is configured and controlled through a set of control/status registers: IN registers EINCSRL and
EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. The endpoint control/status registers are
mapped into the USB register address space based on the contents of the INDEX register (Figure 12.4).
12.12. Controlling Endpoint1 IN
Endpoint1 IN is managed via USB registers EINCSRL and EINCSRH. The IN endpoint can be used for
Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in
register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1 IN interrupt is generated by any of the following conditions:
1. An IN packet is successfully transferred to the host.
2. Software writes ‘1’ to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.
3. Hardware generates a STALL condition.
12.12.1.Endpoint1 IN Interrupt or Bulk Mode
When the ISO bit (EINCSRH.6) is logic 0, Endpoint1 operates in Bulk or Interrupt Mode. Once it has been
configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_INTERFACE com-
mand), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit (EINCSRL.0).
Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and generate an
interrupt.
Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be
transmitted upon reception of the next IN token.
A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EINCSRL.4). While
SDSTL = ‘1’, hardware will respond to all IN requests with a STALL condition. Each time hardware gener-
ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to ‘1’. The
STSTL bit must be reset to ‘0’ by firmware.
Hardware will automatically reset INPRDY to ‘0’ when a packet slot is open in the endpoint FIFO. If double
buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the IN FIFO
at a time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware loads the first packet
into the FIFO and sets INPRDY to ‘1’. An interrupt will not be generated in this case; an interrupt will only
be generated when a data packet is transmitted.
When firmware writes ‘1’ to the FCDT bit (EINCSRH.3), the data toggle for each IN packet will be toggled
continuously, regardless of the handshake received from the host. This feature is typically used by Inter-
rupt endpoints functioning as rate feedback communication for Isochronous endpoints. When FCDT = ‘0’,
the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet.
12.12.2.Endpoint1 IN Isochronous Mode
When the ISO bit (EINCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode. Once
an endpoint has been configured for ISO IN mode, the host will send one IN token (data request) per
frame; the location of data within each frame may vary. Therefore, it is recommended that double buffering
be enabled when using Endpoint1 IN as an Isochronous endpoint.
110
Rev. 0.5