C8051F326 Datasheet, PDF (123/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
13.3. Configuration and Operation
UART0 provides standard asynchronous, full duplex communication. It can operate in a point-to-point
serial communications application, or as a node on a multi-processor serial interface. To operate in a
point-to-point application, where there are only two devices on the serial bus, the MCE0 bit in SMOD0
should be cleared to ‘0’. For operation as part of a multi-processor communications bus, the MCE0 and
XBE0 bits should both be set to ‘1’. In both types of applications, data is transmitted from the microcontrol-
ler on the TX0 pin, and received on the RX0 pin. The TX0 and RX0 pins are configured using the crossbar
and the Port I/O registers, as detailed in Section “11. Port Input/Output” on page 81.
In typical UART communications, The transmit (TX) output of one device is connected to the receive (RX)
input of the other device, either directly or through a bus transceiver, as shown in Figure 13.5.
PC
RS-232
COM Port
RS-232
TX
LEVEL
RX ^C8051Fxxx
TRANSLATOR
OR
TX
MCU
RX
TX
C8051Fxxx
RX
Figure 13.5. Typical UART Interconnect Diagram
13.3.1. Data Transmission
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) will be set at the end of any transmission (the beginning of the stop-bit time). If
enabled, an interrupt will occur when TI0 is set.
If the extra bit function is enabled (XBE0 = ‘1’) and the parity function is disabled (PE0 = ‘0’), the value of
the TBX0 (SCON0.3) bit will be sent in the extra bit position. When the parity function is enabled (PE0 =
‘1’), hardware will generate the parity bit according to the selected parity type (selected with S0PT[1:0]),
and append it to the data field. Note: when parity is enabled, the extra bit function is not available.
13.3.2. Data Reception
Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the
stop bit is received, the data byte will be stored in the receive FIFO if the following conditions are met: the
receive FIFO (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. In the event that the
receive FIFO is full, the incoming byte will be lost, and a Receive FIFO Overrun Error will be generated
(OVR0 in register SCON0 will be set to logic 1). If the stop bit(s) were logic 0, the incoming data will not be
stored in the receive FIFO. If the reception conditions are met, the data is stored in the receive FIFO, and
the RI0 flag will be set. Note: when MCE0 = ‘1’, RI0 will only be set if the extra bit was equal to ‘1’. Data can
be read from the receive FIFO by reading the SBUF0 register. The SBUF0 register represents the oldest
byte in the FIFO. After SBUF0 is read, the next byte in the FIFO is loaded into SBUF0, and space is made
available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI0 is set.
If the extra bit function is enabled (XBE0 = ‘1’) and the parity function is disabled (PE0 = ‘0’), the extra bit
for the oldest byte in the FIFO can be read from the RBX0 bit (SCON0.2). If the extra bit function is not
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