C8051F326 Datasheet, PDF (130/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
14.1.1. Mode 0: 13-bit Timer
Timer 0 and Timer 1 operate as 13-bit timers in Mode 0. The following describes the configuration and
operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same man-
ner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit timer. TL0 holds the five LSBs in bit positions TL0.4-
TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored
when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the
timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled.
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or GATE0 is logic
1 and the input signal /INT0 is active. Setting GATE0 to logic 1 allows the timer to be controlled by the
external input signal /INT0, facilitating pulse width measurements. When GATE0 is set to logic 1, the /INT0
input pin is P0.2.
TR0
GATE0
0
X
1
0
1
1
1
1
X = Don't Care
/INT0
X
X
0 (P0.2 High)
1 (P0.2 Low)
Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled. TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as
described above for TL0 and TH0. Timer 1 is configured and controlled using the relevant TCON and
TMOD bits just as with Timer 0. The input signal /INT1 is used with Timer 1. See Section “8.3.2. External
Interrupts” on page 59 for a complete description of /INT0 and /INT1.
CKCON
T TSS
1 0CC
MMA A
10
Pre-scaled Clock
0
TMOD
GC T TGC T T
A / 11A / 00
T T MM T T MM
E110E010
1
0
SYSCLK
1
TR0
GATE0
/INT0
TCLK
TL0
(5 bits)
TH0
(8 bits)
Figure 14.1. T0 Mode 0 Block Diagram
TF1
TR1
TF0
Interrupt
TR0
IE1
IT1
IE0
IT0
130
Rev. 0.5