C8051F326 Datasheet, PDF (72/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
9.2. Accessing USB FIFO Space
The upper 256 bytes of XRAM functions as USB FIFO space. Figure 9.2 shows an expanded view of the
FIFO space and user XRAM. FIFO space is accessed via USB FIFO registers; see Section “12.5. FIFO
Management” on page 97 for more information on accessing these FIFOs. The FIFO block operates on
the USB clock domain; thus the USB clock must be active when accessing FIFO space.
Important Note: The USB clock must be active when accessing FIFO space.
0x03FF
User XRAM Space
(System Clock Domain)
User XRAM
(1024 bytes)
0xFF
0xC0
0xBF
0x00
Endpoint0
(64 bytes)
IN (64 bytes)
Endpoint1
OUT (128 bytes)
USB FIFO Space
(USB Clock Domain)
0x0000
Figure 9.2. XRAM Memory Map Expanded View
SFR Definition 9.1. EMI0CN: External Memory Interface Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
-
-
PGSEL1 PGSEL0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xAA
Bits7–3:
Bits2–0:
Unused. Read = 000000b. Write = don’t care.
PGSEL[1:0]: XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM. The upper 6-bits are "don't cares", so the 1k address block is repeated modulo over
the entire 64k external data memory address space.
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Rev. 0.5