C8051F326 Datasheet, PDF (63/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
SFR Definition 7.2. RSTSRC: Reset Source
R/W
R
R
USBRSF FERROR —
Bit7
Bit6
Bit5
R/W
SWRSF
Bit4
R
R/W
R/W
R
Reset Value
— MCDRSF PORSF PINRSF Variable
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xEF
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
USBRSF: USB Reset Flag
0: Read: Last reset was not a USB reset; Write: USB resets disabled.
1: Read: Last reset was a USB reset; Write: USB resets enabled.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
UNUSED. Read = 0. Write = don’t care.
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset.
UNUSED. Read = 0. Write = don’t care.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On / VDD Monitor Reset Flag.
This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the VDD
monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled
and stabilized can cause a system reset. See register VDM0CN (Figure 7.1).
0: Read: Last reset was not a power-on or VDD monitor reset; Write: VDD monitor is not a
reset source.
1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indetermi-
nate; Write: VDD monitor is a reset source.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
Note: Do not use read-modify-write instructions on this register.
Rev. 0.5
63