C8051F326 Datasheet, PDF (111/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
Hardware will automatically reset INPRDY (EINCSRL.0) to ‘0’ when a packet slot is open in the endpoint
FIFO. Note that if double buffering is enabled for the endpoint, it is possible for firmware to load two pack-
ets into the IN FIFO at a time. In this case, hardware will reset INPRDY to ‘0’ immediately after firmware
loads the first packet into the FIFO and sets INPRDY to ‘1’. An interrupt will not be generated in this case;
an interrupt will only be generated when a data packet is transmitted.
If there is not a data packet ready in the endpoint FIFO when USB0 receives an IN token from the host,
USB0 will transmit a zero-length data packet and set the UNDRUN bit (EINCSRL.2) to ‘1’.
The ISO Update feature (see Section 12.7) can be useful in starting a double buffered ISO IN endpoint. If
the host has already set up the ISO IN pipe (has begun transmitting IN tokens) when firmware writes the
first data packet to the endpoint FIFO, the next IN token may arrive and the first data packet sent before
firmware has written the second (double buffered) data packet to the FIFO. The ISO Update feature
ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame;
the packet will only be sent after a SOF signal has been received.
Rev. 0.5
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