C8051F326 Datasheet, PDF (24/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F326/7
Name
VDD
VIO
GND
RST/
Pin Numbers
‘F326 ‘F327
Type
Description
Power 2.7–3.6 V Core Supply Voltage Input.
In
6
6
Power 3.3 V Voltage Regulator Output. See Section 5.
Out
Power V I/O Supply Voltage Input. The voltage at this pin must be
5
—
In less than or equal to the Core Supply Voltage (V_DD) for the
'F326. On the 'F327, this pin is internally connected to V_DD.
2
3
Ground.
D I/O Device Reset. Open-drain output of internal POR or VDD
9
9
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See Section 7.
C2CK
P3.0/
C2D
REGIN
VBUS
D+
D–
P0.0
P0.1
P0.2
P0.3/
D I/O Clock signal for the C2 Debug Interface.
D I/O Port 3.0. See Section 11 for a complete description.
10 10
D I/O Bi-directional data signal for the C2 Debug Interface.
7
7
Power 5 V Regulator Input. This pin is the input to the on-chip volt-
In age regulator.
VBUS Sense Input. This pin should be connected to the
8
8
D In VBUS signal of a USB network. A 5 V signal on this pin indi-
cates a USB network connection.
3
4
D I/O USB D+.
4
5
D I/O USB D–.
1
2
D I/O Port 0.0. See Section 11 for a complete description.
28
1
D I/O Port 0.1. See Section 11 for a complete description.
27 28 D I/O Port 0.2. See Section 11 for a complete description.
D I/O Port 0.3. See Section 11 for a complete description.
XTAL2
P0.4
P0.5
26 27
D In External Clock Input. See Section 10 for a complete
description.
25 26 D I/O Port 0.4. See Section 11 for a complete description.
24 25 D I/O Port 0.5. See Section 11 for a complete description.
24
Rev. 0.5