NT68520XF Datasheet, PDF (76/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

DPLL Clock Control
Formula :
Fout = ((N+2) x Fref) / (M+2)
Fref = 12 MHz
NT68520X,E
CFH: DPLL Control(R/W)
Bits Name
D7-2
D1 DPLL_EN
D0
Description
Reserved
Enable DPLL
0: Disable
1: Enable
Reserved
Default: XXXX XX10B
D0H: Reserved
D1H: Reserved
D2H: DPLL VCO Divider –N (R/W)
Bits Name
D7-6 RCZ1 [1:0]
D5-0 DPLL_N [5:0]
Description
DPLL VCO Divider Value (N).
Default: 0000 0000B
This register is double-buffered.
D3H: DPLL VCO Divider –M (R/W)
Bits Name
D7-6 FOA [1:0]
D5-4 VCA [1:0]
D3-0 DPLL_M [3:0]
Description
DPLL VCO Divider Value (M), Writing in this register will load the
double-buffered register D2h to take affect
Default: 0000 0000B
D4H: DPLL Select and Power Up Control (R/W)
Bits Name
D7 PU_APLL
D6 PU_V
D5 EN_FOA
Description
Power up PLL internal circuit
0: Power down
1: Power up
Power up PLL internal circuit
0: Power down
1: Power up
2003/4/15
76
Ver.1.0