NT68520XF Datasheet, PDF (58/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

D5 INS_HPW
D4-0
Pulse Width Selection of inserted Hsync pulse
0: Pulse Width = value HPW[7:0]
1: Pulse Width =1uS
Reserved
Default: 110X XXXXB
NT68520X,E
87H: H/V Sync Input Control (R)
Bits
D7-5
D4 INTERLACE
D3 HS_LVL
D2 VS_LVL
D1 HI_POL
D0 VI_POL
Description
Reserved
Interlace auto-detecting indicator flag.
0: Not interlace input sync
1: Interlace input sync
The input digital level of HSYNCI pin at the sampling moment.(for debug)
0: Low Level
1: High Level
The input digital level of VSYNCI pin at the sampling moment.(for debug)
0: Low Level
1: High Level
H-Polarity Flag Detected by Input Polarity Detection Circuit.
0: Negative polarity. The high period is longer than 60% of input sync period
1: Positive polarity. The low period is longer than 60% of input sync period
V-Polarity Flag Detected by Input Polarity Detection Circuit.
0: Negative polarity. The high period is longer than 60% of input sync period
1: Positive polarity. The low period is longer than 60% of input sync period
Default：XXXX XXXXB
88H: H/V Sync Output Control (R/W)
Bits
Description
D7 EN_HOUT HSYNCO output enable
0: Disable
1: Enable
D6 EN_VOUT VSYNCO output enable
0: Disable
1: Enable
D5 EN_HRUN Free-run horizontal output control
0: Disable
1: Enable
D4 EN_VRUN Free-run vertical output control
0: Disable
1: Enable
D3 EN_INS
Insert Hsync pulse control
0: Disable
1: Enable
D2 SYNCO_SE Source selection control of sync-out (HSYNCO and VSYNCO)
L
0: Sync output from the external sync input pin
1: Sync output from the internal free-run generator.
D1 HO_POL Hsync output polarity control
2003/4/15
58
Ver.1.0