NT68520XF Datasheet, PDF (23/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

NT68520X,E
1
1
32.768 ms
After system reset, this gate interval source will be disabled and the contents of the
HGATE_SRC bits are '0'. When this function is disabled, the HCNT_LB/HB counter is
working on the VSYNC pulse.
Latching the Hsync counter: The counted value will be latched by the HCNT_HB/LB
registers which are updated by Vsync pulse or user’s selected time interval. If the
counter overflows, the HCNTOV bit (in HCNT_HB register) will be set to HIGH. It will not
change until the next counter cycle is completed to update it. That means the HCNTOV
bit will be updated every Gate cycle of Hsync counter.
All counters are with 2-lay content latches for counting sync period/frequency, so users
will get stable counter results even at the latch transient.
VSYNCI
Latch HCNT register
Reset H sync. counter
Start pulse counting
Update HCNTOV
GATE_SRC=0
HSYNCI
HGATE_SRC=0
Latch HCNT register
Reset H sync. counter
Start pulse counting
Update HCNTOV
16.384ms/32.768ms
(HGATE_TME=0/1)
HSYNCI
HGATE_SRC=1
2003/4/15
23
Ver.1.0