NT68520XF Datasheet, PDF (35/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

NT68520X,E
08H: Reserve (R/W)
Bits Name
Description
D7-0
Reserved
Default：XXXX XXXXB
09H: ADC PLL Divider Value - High Byte (R/W)
Bits Name
D7-3
D2-0 DIV[10:8]
Description
Reserved
The high byte[2:0] of PLL divider value. Write this register will transfer the
data of double-buffered register 0AH to the actual position. N divider =
Divider<10:0> + 1
Default：XXXX X101B
0AH: ADC PLL Divider Value - Low Byte (R/W)
Bits Name
D7-0 DIV
[7:0]
Description
The low byte[7:0] of PLL divider value. The register is double-buffered.
N divider = Divider<10:0> + 1
Default：0100 0000B
0BH: Clamp Pulse Control (R/W)
Bits Name
D7-4 Width[3:0]
D3-0 Dly [3:0]
Description
Clamp pulse width control, 0~15 pixel clocks width.
Clamp pulse starting position control, 0~15 pixel clocks away from trailing
edge of Hsync pulse, 0 maps to the first pixel.
Default：0101 0101B
0CH: VCO Gain Control (R/W)
Bits Name
D7-6 Hfrange[1:0]
D5-4 HICP[1:0]
D3-2 RCZ[1:0]
Description
Frequency range
00 : 10~40 Mhz; Kvco~15MHz/V
01 : 37~64 Mhz; Kvco~30Mhz/V
10 : 59~106 Mhz; Kvco~60Mhz/V
11 : 97~167 Mhz; Kvco~100Mhz/V
Charge pump current
00 : 100uA
01 : 200uA
10 : 400uA
11 : 700uA
PLL Low filter internal resister
00 : 8K
01 : 4K
10 : 2K
11 : 1K
2003/4/15
35
Ver.1.0