NT68520XF Datasheet, PDF (57/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

Sync Processor
85H: Clamp Pulse Control (R/W)
Bits Name
Description
D7-4
Reserved
D3 CLMP_EDG Trigger Edge of the Clamp Pulse
0 : Clamp pulse is at the trailing edge of Hsync
1 : Clamp pulse is at the leading edge of Hsync
D2 CLMP_POL Clamp Pulse Polarity Selection
0 : Negative polarity
1 : Positive polarity
D1-0 CLMP_PW[1 Clamp Pulse Width Selection
:0]
00 : 0.25us
01 : 0.5us
10 : 1us
11 : 2us
Default: XXXX 0100B
NT68520X,E
86H: Sync Processor Control (R/W)
Bits Name
Description
D7 EN_FRUN 0: Disable free-run function to save power consumption.
1: Enable free-run function.
D6 AUTO_FLT 0: Disable Auto Filter function
1: Enable Auto Filter function of H/V extract circuit.
D5 EN_SOG SOG function control bit
0: Disable SOGI pin
1: Enable SOGI pin, HSYNCI input will be discarded
D4
Reserved
D3 EN_POL_HI Hsync polarity user programming
D
0 : Disable
1 : Enable
D2 HI_POL_SE Hsync input polarity select
L
0 : Active low
1 : Active high
D1 EN_POL_VI Vsync polarity user programming
D
0 : Disable
1 : Enable
D0 VI_POL_SE Vsync input polarity select
L
0 : Active low
1 : Active high
Default: 000X 0000B
87H: H/V Sync Input Control (W)
Bits
D7-6 SYNCI_SEL
[1:0]
Description
Type Selection of Sync Input
0X: Composite Sync from SOGI pin
10: Composite Sync from HSYNCI or YUV_HS pin
11: Separate Sync from HSYNCI/VSYNCI or YUV_HS/YUV_VS
2003/4/15
57
Ver.1.0