NT68520XF Datasheet, PDF (37/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

11111 ~ 10000 -> 0 ~ -15 (1’s complement)
Default：XXX0 0000B
NT68520X,E
11H: Blue Channel DC Shift Control (R/W)
Bits Name
D7-5
D4-0 Bsf[4:0]
Description
Reserved
Control the B channel DC shift value to compensate the color excursion.
MSB is sign bit.
00000 ~ 01111 -> 0 ~ 15
11111 ~ 10000 -> 0 ~ -15 (1’s complement)
Default：XXX0 0000
CAPTURE INTERFACE
12H: Capture Interface Control (R/W)
Bits Name
Description
D7 FLASH_NOISE Flash noise detection data port, this is a double buffer and write action by
writing
any data to CR1F
1:Enable flash noise detection
D6 INTE_DET_EDG Interlace detecting edge to work with CR94H to detect the ODD/EVEN
E
filed
0 : Falling edge.
1 : Rising Edge. use the normalized Vsync rising edge.
D5-4
Reserve
D3 CAPCLK_POL Invert the polarity of Pixel Clock from external YUV decoder or internal
ADCPLL
1: Invert
0: Normal
D2 YUV_SWAP Swap the Y & UV byte from external YUV decoder
1: Swap
0: Normal
D1 VIDEO_SEL Select video input source
1: From digital YUV input port, VGA circuit entering power- down
0: From analog VGA input port, YUV circuit entering power- down
D0 CAPCLK_SEL Capture clock source select
0: Internal clock, from PLL
1: External clock, from YUV_CLK pin
Default：X0XX 0000B
13H: Capture VGA and YUV Control (R/W)
Bits Name
D7-6
D5-4 DEINTE_SEL
[1:0]
Description
Reserved
Select the de-interlace method to display for interlace input
11: Spatial interpolation.
10: Display only even field.
01: Display only odd field.
00: Display both odd and even field.
2003/4/15
37
Ver.1.0