NT68520XF Datasheet, PDF (25/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

f_VSYNC
(SEP)
Vsync Frequency from
Separate VSYNCI input for
Sync Processor
t_VPW(SE
P)
t_VPW(C
OMP)
f_HSYNC
VSYNC input Pulse Width
of Separate SYNC
VSYNC input pulse width of
Composite/SOG SYNC
Hsync Input Frequency
t_HPW(SE
P)
t_HPW(C
OMP)
HSYNC input Pulse Width
of Separate-Type SYNC
HSYNC input Pulse Width
of Composite/SOG SYNC
15
0.150
0.150
15
0.150
0.150
NT68520X,E
-
250
Hz
Vsync Duty Cycle
= 40%
-
32000
us
Vsync Duty Cycle
< 40%
-
2000
us
Vsync Duty Cycle
< 40%
- 250 KH Hsync Duty Cycle
z = 40%
-
85
us
Hsync Duty Cycle
< 40%
-
20.8
us
Hsync Duty Cycle
< 40%
Positive Polarity
t_PW < T * 40%
Negative Polarity
T = Period
t_PW = Pulse Width
Polarity Definition of the Sync Pulse
Clamp Pulse Output
A block circuit called clamp pulse generator generates clamp pulse on the CLMPO,
and outputs it to the video Pre-Amplifier for DC restoration. There are two input trigger
sources of the clamp generator, one is the signal HSYNCI from separator and another is
H_FREE from the internal free-run block. If the bit SYNCO_SEL is 1 then the Hin input
source will be selected, otherwise the H_FREE will be selected. The polarity and the trigger
edge of the CLMPO can be selected by using bit CLMP_POL and bit CLMP_EDG
respectively. The trigger delay of the CLMPO (td_clmp) is less than 50ns. It is a fixed
delay and independent from the input video timing. The output transient of the CLMPO
will not cause any crosstalk and phase jitter. The pulse width of the CLMPO output may
be selected by bit CLMP_PW0 and bit CLMP_PW1. Refer to the description of the
CLMP_REG for details.
2003/4/15
25
Ver.1.0