NT68520XF Datasheet, PDF (24/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

Extract Vsync from Composite/SOG Signal
NT68520X,E
Vsync
Hsync
ORed
XORed
Single
Serrated
Double
Serrated + Equal.
Extracted VSYNCO
Extracted HSYNCO
from SOGI
EN_INST=1
Extracted HSYNCO
from HSYNCI
EN_INST=1
Pre-Equal. Pulses
Serration Pulses
Post-Equal. Pulses
Vertical Blanking Interval
t_{extract(VSYNCO)} = fixed
t_PW(insert)
t_{widen(VSYNCO)}
Inserted Pulses
t_PW(insert)
Inserted Pulses
H/V Sync Timing
Polarity Detection
The sync polarity detection circuit will measure the length of high period of sync and the
length of the low period of sync. If the length of the low period is longer than 60% of the
input sync period, the input polarity bit (HI_POL or VI_POL) will be one, indicating a
positive polarity. If the length of the low period is shorter than 40% of the input sync
period, the input polarity will be zero, indicating a negative polarity. The specifications of
the polarity detection circuit are listed below.
Spec. Table of H/V Polarity Detect Unit
2003/4/15
24
Ver.1.0