NT68520XF Datasheet, PDF (47/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

NT68520X,E
DISPLAY INTERFACE
4CH: Display Control (R/W)
Bits Name
Description
D7 AUTO_SYNC_LO Auto Capture Synchronous Lock position stop
CK_EN
0: Disable
1: Enable
D6 DISP_AUTO
Decide the working mode of Display Horizontal Timing generation.
0: Manual mode. H/W automatically adjusts the VT and VFP timings,
others
fully depend on Reg4EH ~ Reg5DH. Capture Synchronous Lock
Position
= Reg1CH ~ Reg1DH
1: Auto mode. H/W automatically adjusts the HT(only once), HFP, VT,
VFP.
H/W automatically adjusts Capture Synchronous Lock position, but can
be
Disabled by 4CH(D7)
D5 DISP_AUTO_STE Decide the H-total adjust value even step
P_HT_EVEN_ON 0 : Disable
LY
1 : Enable
D4 SKEW
Skew output control for double pixel display.
D3 DISP_EN
Display Enable
0: Disable. Tri-state control lines and data lines.
1: Enable
D2 DISP_CD
Display Color Depth
0: 8-bit/color
1: 6-bit/color
D1 DISP_BW
Display Bus Width
0: Double pixel 48-bit
1: Single pixel 24-bit(A group)
D0 DISP_DE
Panel DE Mode Support
0: Panel supports Sync mode, display Hs/Vs signal is at normal state
1: Panel supports DE mode, display Hs/Vs signals will be pulled LOW or
HIGH, it
depends on REG 61H(D1-0), if DISP_HS_POL = 0 and DISP_VS_POL
= 1,
then Hs is pulled to LOW, and Vs is pulled to HIGH
Default：0000 0000B
4DH: Display Mute Control (R/W)
Bits Name
D7 BYPASS
D6 MUTE_AUTO
D5
Description
Enable the captured data by-passing the scaler
0: Normal
1: Bypass
Mute with OSD when VGA input sync fail
0: Disable
1: Enable
Reserved
2003/4/15
47
Ver.1.0