NT68520XF Datasheet, PDF (38/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

NT68520X,E
D3 CAP_HS_SOU Decide the Hsync pulse source referenced by capture circuit
0: From external HSYNCI pin
1: From internal re-synchronized Hs(re-sync by CAPTURE CLOCK
falling edge)
D2 FIELD_POL
Invert the polarity of input Field signal. Field signal ‘1’ is considered as
ODD field
1: Invert
0: Normal
D1 FIELD_SEL
Field Indicator Source Select
1: From YUV656 decoded FIELD signal.
0: From Internal Synchronization Processor detected FIELD signal
D0 INTE_SEL
Interlace or non-interlace input select
1: Interlace
0: Non-interlace
Default：XX00 0000B
14H: Capture Vertical Start - Low Byte (R/W)
Bits Name
Description
D7-0 CAP_VS [7:0] Define the low byte[7:0] of the start position of the input vertical active
window. This register is double-buffered by REG 15H.
Default：0000 0000B
15H: Capture Vertical Start - High Byte (R/W) and Capture Vertical Start Shift in
odd/even field (works in interlace mode, CR13, D0 =1)(R/W)
Bits Name
Description
D7 FIELD_CAP_SH_EN Enable either ODD or EVEN field Vertical Capture Start shift 1 line
0: Enable
1: Disable
D6 FIELD_CAP_SH_SE Select the Field to shift vertical capture start
L
1: ODD field
0: EVEN field
D5 CAP_VS_SH_EN Enable either ODD or EVEN field Capture Vertical Sync. pulse shift 1
line
0: Enable
1: Disable
D4 CAP_VS_SH_SEL Select the Field to shift Capture Vertical Synchronization pulse
1: ODD field
0: EVEN field
D3
Reserved
D2-0 CAP_VS [10:8]
Define the high byte[10:8] of the start position of the input vertical
active window. Write this register will transfer the data of
double-buffered register 14H to the actual position.
Default：0000 X000B
16H: Capture Vertical Height - Low Byte (R/W)
Bits Name
Description
2003/4/15
38
Ver.1.0