NT68520XF Datasheet, PDF (26/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

Clamp Pulse Timing
NT68520X,E
HSYNCI / H_FREE
Positive Polarity
HSYNCI / H_FREE
Negative Polarity
CLMPO
CLMP_EDG=1
CLMP_POL=1
CLMPO
CLMP_EDG=0
CLMP_POL=1
CLMPO
CLMP_EDG=1
CLMP_POL=0
CLMPO
CLMP_EDG=0
CLMP_POL=0
t_{PW_CLMP}
Leading Edge
Trailing Edge
t_{D_CLMP}
Clamp Pulse Timing
Free Running
This Block can generate various free-running outputs to satisfy various application
requirements. The pulse width of the H_FREE output is fixed to 1us and the V_FREE is 8 lines.
Users can properly set the contents of the dot counters, DCNT_HB and DCNT_LB, to
get the required frequency of the H_REEE, and set the contents of the line counters,
LCNT_HB and LCNT_LB, to get the frequency of the V_FREE. Refer to the descriptions of
the free-run registers DCNT_HB, DCNT_LB, LCNT_HB, and LCNT_LB for details. Refer
to the descriptions of the DCNT register and the LCNT register for obtaining user’s
required frequencies in details.
The EN_FRUN bit can gate the 12MHz clock source to disable this block function and to
save power consumption. The previous values will be preloaded into the DCNT/LCNT
counters from the DCNT_HB, LB / LCNT_HB, LB at the transient of EN_FRUN from 0 to
1. Users also can disable the H/V free run output by clearing the EN_HRUN /
EN_VRUN.
When you want to set the H/V free-running frequency, remember to set the high byte
2003/4/15
26
Ver.1.0