NT68520XF Datasheet, PDF (62/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

D3 INTUNDER_E 1: Enable INT_UNDER interrupt
N
0: Disable
D2 INTHP_EN 1: Enable INT_HP interrupt
0: Disable
D1 INTVP_EN 1: Enable INT_VP interrupt
0: Disable
D0 INTFM_EN 1: Enable INT_FM interrupt
0: Disable
Default: 00X0 0000B
NT68520X,E
93H: Fast Mute Control (W)
Bits Name
D7 UPD_HT
D6 AUTO_UPD
D5 VINT_POL
D4 HINT_POL
D3-2 DIFF_CNT
[1:0]
D1-0 DIFF_VAL
[1:0]
Description
This bit is controlled by S/W if AUTO_UPD=0.
0: Hold B
1: Update B from A per Hsync; see Fast Mute block diagram
0: Manually control the UPD_HT bit
1: H/W automatically sets UPD_HT to update B from A when the fast mute
occurs, then it clears UPD_HT after the input Hsync has been stable for at
least 3mS.
Invert the internal V-sync polarity. (for debug)
0: Normal
1: Invert
Invert the internal H-sync polarity. (for debug)
0: Normal
1: Invert
The FAST MUTE will occur if the number of times out of DIFF_VAL are larger
than the DIFF_CNT setting.
00: 4 times
01: 8 times
10: 16 times
11: 32 times
Difference Boundary of the H-Period Counter
00: 4 counts
01: 8 counts
10: 16 counts
11: Reserved
Default: 11XX 0101B
93H: Fast Mute Control (R)
Bits Name
D7-6
D5 HS_ACT
D4 VS_ACT
D3-0
Description
Reserved
0: No Hsync in 3mS interval. (for debug)
1: Hsync is active.
0: No Vsync in 132mS interval. (for debug)
1: Vsync is active.
Reserved
2003/4/15
62
Ver.1.0