NT68520XF Datasheet, PDF (22/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

NT68520X,E
1
1
Separate Sync from
HSYNCI/VSYNCI
Frequency detection
Vsync counter: VCNT [13:0], the 14-bit READ ONLY register, contains information of
the Vsync frequency. An internal counter counts the numbers of 8us pulse between two
VSYNC pulses. When a next VSYNC signal is recognized, the counter is stopped and
the VCNT register latches the counter value and then the counter counts from zero again
for evaluating the next VSYNC time interval. The counted data can be converted to the
time duration between two successive Vsync pulses by timing 8 us. If no VSYNC comes
in, the counter will overflow and set the VCNTOV bit (in VCNT_HB register) to HIGH.
Once the VCNTOV is set to HIGH, it will remain unchanged until the next counter cycle
is completed for its update. That means the VCNTOV bit will be updated every Vsync
Counter cycle. It is necessary for various applications to provide various overflow time
intervals. They are selectable as shown in the following table.
VOV_SEL1 VOV_SEL0
0
0
0
1
1
0
1
1
Time
Interval
32.768ms
65.536ms
98.304ms
131.072ms
Hsync counter: If the HGATE_SRC bit is set to Low, the internal counter counts the
Hsync pulses between two Vsync pulses. The HCNT [11:0] control registers contain the
numbers of Hsync pulse between two Vsync pulses. These data can determine if the
Hsync frequency is valid or not to determine the accurate video mode. The system
supports two other options of intervals for users to count the frequency of Hsync pulses.
If users set the HGAT_SRC and the HGATE_TME bits properly, the internal counter
counts the Hsync pulses during this system defined time interval. The time interval is
defined below:
HGATE_SR
C
0
HGATE_TM
E
-
Gate Time
Vsync
Period
1
0
16.384 ms
2003/4/15
22
Ver.1.0