NT68520XF Datasheet, PDF (33/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

NT68520X,E
Register Summary
SCALER
POWER CONTROL
00H: Power Down Control (R/W)
Bits Name
D7-1
D0 SYS_PD
Description
Reserved
System Power Down Enable
0: Disable
1: Enable
Default：XXXX XXX0B
ADC INTERFACE
01H: ADCPLL Control (R/W)
Bits Name
D7 EN_intclp
D6 CoastINV
D5-4
D3 COAST_EN
D2 HI_POL_SEL
D1 REGvref
D0 CAP_CLK_EN
Description
Clamp pulse source selection
0 : External clamp pulse.
1 : Internal clamp pulse.
ADC coast inverter
0 : Non-inverter.
1 : Inverter.
Reserve
COAST function enable
0: Disable
1: Enable
ADC Hsync input polarity select
0 : Non-invert polarity
1 : Invert polarity
ADCPLL reference voltage(2.5V) source select
0 : External (from VREF pin)
1 : Internal (from internal regulator)
Capture clock enable
0: Disable PLL output
1: Enable PLL output
Default：00XX 0101B
02H: Red Channel Gain Control (R/W)
Bits Name
D7-0 RGAIN[7:0]
Description
The gain range from 0.8 to 2.0 for R-channel, the register is defined by
8-bits to produce 1V(p-p) output signal for ADC input. R_Gain = 0.8 +
1.2/255 * D[7:0]
Default：0000 0000B
2003/4/15
33
Ver.1.0