NT68520XF Datasheet, PDF (14/97 Pages) List of Unclassifed Manufacturers – XGA,SXGA Flat Panel Monitor Controller

NT68520X,E
FUNCTION DESCRIPTION
VGA Front End
The NT68520 provides a built-in video pre-amplifier, a clock-recovery circuit and an
analog-to-digital converter to effectively save the cost of the required external expensive
Pre-amp and ADCPLL.
The pre-amplifier circuit is used to adjust the gain (Contrast) of input video amplitude and
shift the DC offset voltage (Brightness).
The clock-recovery circuit consisting of a high-speed phase lock loop (PLL) is used to
generate the clock to sample analog RGB data. This circuit is locked to the HSYNC of
the incoming video signal.
The analog-to-digital converter (ADC) transfers the input analog RGB video to digital
output data with each color 8-bit resolution.
Pre-amplifier Unit
RIN/GIN/BIN are high-impedance input pins that accept the RED, GREEN, and BLUE
channel graphics signals. They accommodate input signals ranging from 0.5V to 1.0V
full scale. Signals should be AC-couple to these pins.
Due to AC coupling, clamping pulse is needed to define the time during which the input
signal is clamped to ground, establishing a black reference. Typically, the clamping pulse
is defined during the back porch period of the graphics signal. The NT68520 generates
the clamping pulse internally and the position and duration are programmable. Clamping
pulse-starting position is defined in register 0B[3:0], and pulse width is defined in 0B[7:4].
T_{CLP_Delay} = Reg0B[3:0] * CKOUT
T_{CLP_Width} = Reg0B[7:4] * CKOUT
Hsync
Clamping Pulse
TCLP_Delay
TCLP_Width
The NT68520 has three independent variable gain amplifiers for each channel with input
2003/4/15
14
Ver.1.0