IBIS4-6600 Datasheet, PDF (45/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
Pin Pin name
45 VDD_RESET_DS
46 ADC_CLK_EXT
47 EOL
48 EOF
49 PIX_VALID
50 TEMP
51 ADC_D<9>
52 VDD_PIX
53 GND_AB
54 ADC_D<8>
55 ADC_D<7>
56 ADC_D<6>
57 ADC_D<5>
58 ADC_D<4>
59 ADC_D<3>
60 VDD_RESET
61 ADC_D<2>
62 ADC_D<1>
63 ADC_D<0>
64 BS_RESET
65 BS_CLOCK
66 BS_DIN
67 BS_BUS
68 CMD_DEC
Pin
type
Power
Input
Output
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Output
Output
Power
Output
Output
Output
Input
Input
Input
Output
Input
Expected
Voltage [V]
2.5 (for no
dual slope)
-
-
-
-
-
-
2.5
0
-
-
-
-
-
-
2.5
-
-
-
-
-
-
-
0.74
Pin description
Variable reset voltage (dual slope).
External ADC clock.
Diagnostic end of line signal (produced
by sequencer), can be used as Y_CLK.
Diagnostic end of frame signal
(produced by sequencer), can be used
as Y_START.
Diagnostic signal. High during pixel
readout.
Temperature measurement. Output
voltage varies linearly with
temperature.
ADC data output (MSB).
VDD of pixel core [2.5 V].
Anti-blooming ground. Set to 1 V for
improved anti-blooming behavior.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
ADC data output.
Reset voltage [2.5 V]. Highest voltage
to the chip. 3.3 V for extended dynamic
range or ‘hard reset’.
ADC data output.
ADC data output.
ADC data output (LSB).
Boundary scan (allows debugging of
internal nodes): reset.
Boundary scan (allows debugging of
internal nodes): clock.
Boundary scan (allows debugging of
internal nodes): in.
Boundary scan (allows debugging of
internal nodes): bus.
Biasing of X and Y decoder. Connect
to VDDD with R = 50 kΩ and decouple
to GNDD with C = 100 nF.
Note on power-on behavior
At power-on, the chip is in an undefined state. It is advised that the power-on is
accompanied by the assertion of the SYS_CLOCK and a SYS_RESET pulse that puts all
internal registers in their default state (all bits are set to 0). The X-shift registers are in
a defined state after the first X_SYNC which occurs a few microseconds after the first
Y_START and Y_CLOCK pulse. Prior to this X_SYNC, the chip may draw more current
from the analog power supply VDDA. It is therefore favorable to have separate analog
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05708 Rev.**(Revision 1.3 )
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