IBIS4-6600 Datasheet, PDF (42/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
4.3.3 ADC timing
4.3.3.a Two analog outputs
Figure 25: ADC timing using two analog outputs
Figure 25 shows the timing of the ADC using two analog outputs. Internally, the
ADCs sample on the falling edge of the ADC_CLOCK (in case of internal clock, the
clock is half the SYS_CLOCK).
T₁ Each ADC has a pipeline delay of 2 ADC_CLOCK cycles. This results in a total
pipeline delay of 4 pixels.
4.3.3.b One analog output
Figure 26: ADC timing with using analog output
Figure 26 shows the timing of the ADC using one analog output. Internally, the ADC
samples on the falling edge of the ADC_CLOCK.
T₁ The ADC has a pipeline delay of 2 ADC_CLOCK cycles.
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