IBIS4-6600 Datasheet, PDF (30/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
Register Bit
4
Name
EXT_CLK
5
TRISTATE
6:8
DELAY_CLK_ADC
9
GAMMA
10
BITINVERT
13 (1101)
14 (1110)
15 (1111)
Reserved.
Reserved.
Reserved.
Description
0 = internal clock (same as clock to X shift
register and output amplifier)
1 = external clock
0 = normal operation
1 = outputs in tristate mode
Delay of clock to ADCs and digital multiplexer
0 = linear conversion
1 = ‘gamma’ law conversion
0 = no inversion of bits
1 = inversion of bits
3.9.2 Detailed description of registers
3.9.2.a SEQUENCER register
3.9.2.a.1 NDR (bit 0)
In normal operation (NDR = 0), the sensor operates in double sampling mode. At the
start of each row readout, the signals from the pixels are sampled, the row is reset and
the signals from the pixels are sampled again. The values are subtracted in the output
amplifier.
When NDR is set to 1, the sensor operates in non-destructive readout (NDR) mode
(see 3.8.2).
3.9.2.a.2 NDR_mode (bit 1 and 2)
These bits only influence the operation of the sensor in case NDR (bit 0) is set to 1.
There are basically two modes for non-destructive readout (mode 1 and 2). Each
mode needs two different frame readouts (setting 1 and 2 for mode 1, setting 3 and 4
for mode 2). First a reset/readout sequence (called reset_seq hereafter) and then one
or several pure readout sequences (called read_seq hereafter). Table 13 shows an
overview of the different NDR modes.
Table 13: Overview of NDR modes.
Setting Bits NDR mode sequence
1 00
1
reset
2 01
1
read
3 10
2
reset
4 11
2
read
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05708 Rev.**(Revision 1.3 )
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