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IBIS4-6600 Datasheet, PDF (36/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor
IBIS4-6600
Datasheet
3.9.2.i.4 Standby
If STANDBY = 1, the complete output amplifier is put in standby (this reduces the
power consumption significantly)
3.9.2.i.5 Delay_clk_amp
The clock that acts on the output amplifier can be delayed to compensate for any
delay that is introduced in the path from shift register, column selection logic, column
amplifier and busses to the output amplifier. Setting ‘000’ is used as a baseline.
Table 16: Delay added by changing the settings of the DELAY_CLK_AMP bits
bits Delay [ns] bits Delay [ns]
000 1.7 100 Inversion + 8.3
001 2.9 101 Inversion + 9.7
010 4.3 110 Inversion + 11.1
011 6.1 111 Inversion + 12.3
3.9.2.j DAC_RAW_REG and DAC_FINE_REG register
These registers determine the black reference level at the output of the output
amplifier. Bit setting 11111111 for DAC_RAW_REG register gives the highest offset
voltage; bit setting 00000000 for DAC_RAW_REG register gives the lowest offset
voltage. Ideally, if the two output paths have no offset mismatch, the DAC_FINE_REG
register must be set to 10000000. Deviation from this value can be used to
compensate the internal mismatch (see 3.5.4).
3.9.2.k DAC_RAW_DARK register
This register determines the voltage level that is put on the internal busses during
calibration of the output stage. This voltage level is also continuously put on the reset
busses in case of non-destructive readout (as a reset level for the double sampling
FPN correction).
3.9.2.l ADC register
3.9.2.l.1 Standby_1 and standby_2
In case only one or none of the ADCs is used, the other or both ADCs can be put in
standby by setting the bit to 1 (this reduces the power consumption significantly).
3.9.2.l.2 One
In case OUT1 and OUT2 are both used and connected to ADC_IN1 and ADC_IN2
respectively, ONE must be 0 to use both ADCs and to multiplex their output to
ADC_D<9:0>. If ONE = 1, the multiplexing is disabled.
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