IBIS4-6600 Datasheet, PDF (15/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
Example: read out time of the full resolution at nominal speed (40 MHz pixel rate):
=> Frame period = (3002 * (7.2 µs + 25 ns * 2210)) = 187.5 ms => 5.33 fps.
3.4 Region-Of-Interest (ROI) read out
Windowing can easily be achieved by uploading the starting point of the x- and y-
shift registers in the sensor registers (see 3.10). This downloaded starting point
initiates the shift register in the x- and y-direction triggered by the Y_START (initiates
the Y-shift register) and the Y_CLK (initiates the X-shift register) pulse. The
minimum step size for the x-address is 24 (only even start addresses can be chosen)
and 1 for the Y-address (every line can be addressed). The frame rate increases almost
linearly when fewer pixels are read out. Table 7 gives an overview of the achievable
frame rates with ROI read out.
Table 7: Frame rate vs. resolution
Image Resolution
(Y*X)
3002 x 2210
1501 x 1104
640 x 480
Frame rate
[frames/s]
Frame readout
time [ms]
Comment
5
187.5
Full resolution.
14
67
ROI read out.
89
11
ROI read out.
3.5 Output amplifier
The output amplifier subtracts the reset and signal voltages from each other to cancel
FPN as much as possible (Figure 8). The DAC that is used for offset adjustment
consists of 2 DACs. One is used for the main offset (DAC_raw) and the other allows
for fine tuning to compensate the offset difference between the signal paths arriving at
the two amplifiers A1 and A2 (DAC_fine). With the analog multiplexer the signals S1
and S2 from the two busses can be combined to one pixel output at full pixel rate (40
MHz). The two analog signals S1 and S2 can, however, also be available on two
separate output pins to allow a higher pixel rate.
The third DAC (DAC_dark) puts its value on the busses during the calibration of the
output amplifier. In case of non-destructive readout (no double sampling), bus1_R
and bus2_R are continuously connected to the output of the DAC_fine to provide a
reference for the signals on bus1_S and bus2_S.
The complete output amplifier can be put in standby by setting the corresponding bit
in the AMPLIFIER register.
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05708 Rev.**(Revision 1.3 )
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