IBIS4-6600 Datasheet, PDF (37/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
3.9.2.l.3 Switch
In case the two ADCs are used (ONE = 0) and internal pixel clock (EXT_CLK = 0), the
ADC output is delayed with one system clock cycle if SWITCH = 1. In case the two
ADCs are used (ONE = 0) and an external ADC clock (EXT_CLK = 1) is applied, the
ADC output is delayed with half ADC clock cycle if SWITCH = 1.
In case only one ADC is used, the digital multiplexing is disabled by ONE = 1, but
SWITCH selects which ADC output is on ADC_D<9:0> (SWITCH = 0: ADC_1,
SWITCH = 1: ADC_2).
3.9.2.l.4 Ext_clk
In case EXT_CLK = 0, the internal pixel clock (that drives the X-shift registers and
output amplifier, i.e. half the system clock) is used as input for the ADC clock. In case
EXT_CLK = 1, an external clock must be applied to pin ADC_CLK_EXT (pin 46).
3.9.2.l.5 Tristate
In case TRISTATE = 1, the ADC_D<9:0> outputs are in tri-state mode.
3.9.2.l.6 Delay_clk_adc
The clock that finally acts on the ADCs can be delayed to compensate for any delay
that is introduced in the path from the analog outputs to the input stage of the ADCs.
The same settings apply as for the delay that can be given to the clock acting on the
output amplifier (see Table 16). The best setting will also depend on the delay of the
output amplifier clock and the load of the output amplifier. It must be used to
optimize the sampling moment of the ADCs with respect to the analog pixel input
signals. Setting ‘000’ is used as a baseline.
3.9.2.l.7 Gamma
If GAMMA is set to 0, the ADC input to output conversion is linear, otherwise the
conversion follows a ‘gamma’ law (more contrast in dark parts of the window, lower
contrast in the bright parts).
3.9.2.l.8 Bitinvert
If BITINVERT = 0, 0000000000 is the conversion of the lowest possible input voltage,
otherwise the bits are inverted.
3.9.3 Serial to Parallel interface
To upload the sequencer registers a dedicated serial to parallel interface (SPI) is
implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. The
address must be uploaded first (MSB first), then the data (also MSB first).
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05708 Rev.**(Revision 1.3 )
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