IBIS4-6600 Datasheet, PDF (33/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
01
4 x sys_clock 282 x T_{SYS_CLOCK}
7.05
10
8 x sys_clock 562 x T_{SYS_CLOCK}
14.05
11
16 x sys_clock
1122 x
28.05
3.9.2.a.8 Black (bit 10)
In case BLACK is set to 1, the internal black signal will be held high continuously. As
a consequence, the column amplifiers are disconnected from the busses, the busses are
set to the voltage given by DAC_DARK and the output of the amplifier equals the
voltages from the offset DACs.
3.9.2.a.9 Reset_all (bit 11)
In case RESET_ALL is set to 1, all the pixels are simultaneously put in a ‘reset’ state. In
this state, the pixels behave logarithmically with light intensity. If this state is
combined with one of the NDR modes, the sensor can be used in a non-integrating,
logarithmic mode with high dynamic range.
3.9.2.b NROF_PIXELS register
After the internal X_SYNC is generated (start of the pixel readout of a particular row),
the PIXEL_VALID signal goes high. The PIXEL_VALID signal goes low when the pixel
counter reaches the value loaded in the NROF_PIXEL register and an EOL pulse is
generated. Due to the fact that 2 pixels are addressed at each internal clock cycle the
amount of pixels read out in one row = 2*(NROF_PIXEL + 1).
3.9.2.c NROF_LINES register
After the internal YL_SYNC is generated (start of the frame readout with Y_START),
the line counter increases with each Y_CLOCK pulse until it reaches the value loaded
in the NROF_LINES register and an EOF pulse is generated. In NDR mode 2, the line
counter increments only every two Y_CLOCK pulses and the EOF pulse shows up only
after the readout of the row indicated by the right shift register.
3.9.2.d INT_TIME register
When the Y_START pulse is applied (start of the frame readout), the sequencer will
generate the YL_SYNC pulse for the left Y-shift register. This loads the left Y-shift
register with the pointer loaded in Y_REG register. At each Y_CLOCK pulse, the
pointer shifts to the next row and the integration time counter increases (increment
only every two Y_CLOCK pulses in NDR mode 2) until it reaches the value loaded in
the INT_TIME register. At that moment, the YR_SYNC pulse for the right Y-shift
register is generated which loads the right Y-shift register with the pointer loaded in
Y_REG
register
(Figure
18).
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05708 Rev.**(Revision 1.3 )
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