IBIS4-6600 Datasheet, PDF (11/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
3 Sensor architecture and operation
In this part of the document some of the more important specifications will be
discussed more detail.
3.1 Floor plan
SENSOR
IMAGE CORE
pixel array
2210 x 3002
(excl. dark +
dummy pixels)
clk_x
sync_x
Dig. logic
Pixel (0,0)
column amplifiers
addressable x-shift register + sub-sampling
address &
data bus
SPI
DAC
DAC in
Dig. logic
analog output (2)
Figure 3: Block diagram of the IBIS4-6600 CMOS image sensor
Figure 3 shows the architecture of the image sensor that has been designed. It consists
basically of the pixel array, shift registers for the readout in x and y direction, parallel
analog output amplifiers, and column amplifiers that correct for the fixed pattern
noise caused by threshold voltage non-uniformities. Reading out the pixel array starts
by applying a y clock pulse to select a new row, followed by a calibration sequence to
calibrate the column amplifiers (row blanking time). Depending on external bias
resistors and timing, typically this sequence takes about 7 µs per line (baseline). This
sequence is necessary to remove the Fixed Pattern Noise of the pixel and of the
column amplifiers themselves (by means of a Double Sampling technique). Pixels can
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05708 Rev.**(Revision 1.3 )
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