IBIS4-6600 Datasheet, PDF (34/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
Sync of left
shift-register
Line n
Sync of right
shift-register
Last line, followed by sync
of left shift-register
Sync
T_{reg_int}
T_int
Figure 18: Syncing of the Y-shift registers.
T_{reg_int} Difference between left and right pointer = integration counter until value “n”
of INT_TIME register is reached = INT_TIME register.
In case of NDR = 0, the actual integration time T_int is given by
T_int Integration time [# lines] = NROF_LINES register - INT_TIME register + 1
In case of NDR = 1, NDR mode 1, the time T_int between two readings of the same row
is given by
T_int Integration time [# lines] = NROF_LINES register + 1
In case of NDR = 1, NDR mode 2, the times T_int1 and T_int2 between two readings of
the same row (alternatingly) are given by
T_int1 Integration time [# lines] = 2 * INT_TIME register + 1
T_int2 Integration time [# lines]
= 2 * (NROF_LINES register + 1) – (2 * INT_TIME register + 1)
3.9.2.e DELAY register
The DELAY register can be used to delay the PIXEL_VALID pulse (bits 0:3) and the
EOL/EOF pulses (bits 4:7) to synchronize them to the real pixel values at the analog
output or the ADC output (which give additional delays depending on their settings).
The bit settings and corresponding delay is indicated in Table 15.
Table 15: Delay added by changing the settings of the DELAY register
bits
0000
0001
0010
0011
0100
0101
Delay [# SYS_CLOCK periods]
0
0
0
1
2
3
bits
1000
1001
1010
1011
1100
1101
Delay [# SYS_CLOCK periods]
6
7
8
9
10
11
Cypress Semiconductor Corporation 3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05708 Rev.**(Revision 1.3 )
Page 34 of 63