IBIS4-6600 Datasheet, PDF (40/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
Figure 22: Basic frame and line timing.
The pulse width of Y_CLOCK should be minimum 1 clock cycle and 3 clock cycles for
Y_START. As long as Y_CLOCK is applied, the sequencer stays in a suspended state.
T₁ Row blanking time: During this period, the X-sequencer generates the control
signals to sample the pixel signal and pixel reset levels, and start the readout
of one line. It depends on the granularity of the X-sequencer clock (see Table
14).
T₂ Pixels counted by pixel counter until the value of NROF_PIXELS register is
reached. PIXEL_VALID goes high when the internal X_SYNC signal is
generated, in other words when the readout of the pixels is started.
PIXEL_VALID goes low when the pixel counter reaches the value loaded in the
NROF_PIXELS register. EOL goes high SYS_CLOCK cycle after the falling edge
of PIXEL_VALID.
T₃ EOF goes high when the line counter reaches the value loaded in the
NROF_LINES register and the line is read (PIXEL_VALID goes low).
Both EOF and EOL can be tied to Y_START (EOF) and Y_CLOCK (EOL) if both signals
are delayed with at least 2 SYS_CLOCK periods to let the sensor run in a fully
automatic way.
4.3 Pixel output timing
4.3.1 Two outputs
The pixel signal at the OUT1 (OUT2) output becomes valid after 4 SYS_CLOCK cycles
when the internal X_SYNC (= start of PIXEL_VALID output) has appeared (see Figure
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