IBIS4-6600 Datasheet, PDF (12/63 Pages) Cypress Semiconductor – High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor

IBIS4-6600
Datasheet
also be read out in a non-destructive manner. Two DACs have been added to make
the offset level of the pixel values adjustable and equal for the two output busses. A
third DAC is used to connect the busses to a stable voltage during the row blanking
period (or to the reset busses continuously in case of non-destructive readout). Two
10-bit ADCs running at 20 Msamples/s will convert the analog pixel values. The
digital outputs will be multiplexed to 1 digital 10-bit output at 40 Msamples/s. Note
that these blocks are electrically completely isolated from the sensor part (except for
the multiplexer for which the settings are uploaded through the shared address and
data bus).
The x and y shift registers do have a programmable starting point. The starting points
possibilities are limited due to limitations imposed by sub-sampling requirements.
The upload of the start address is done through the serial to parallel interface.
Most of the signals for the image core in Figure 3 are generated on chip by the
sequencer. This sequencer also allows running the sensor in basic modes, not fully
autonomously.
3.2 Pixel
3.2.1 Architecture
The pixel architecture is the classical three-transistor pixel as shown in Figure 4. The
pixel has been implemented using the high fill factor technique as patented by
FillFactory (US patent No. 6,225,670 and others).
Vdd
reset
M1
select
M2
output
M3
(column)
Figure 4: Architecture of the 3T-pixel
3.2.2 FPN and PRNU
Fixed Pattern Noise correction is done on chip. Raw images taken by the sensor
typically feature a residual (local) FPN of 0.35 % RMS of the saturation voltage.
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408-943-2600
Contact: [e-mail] Document #: 38-05708 Rev.**(Revision 1.3 )
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