S6E2C2 Datasheet, PDF (180/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
Slave Mode Timing
Parameter
Symbol Pin Name
Input frequency
Input clock pulse width
I2SWS→I2SCK
Setup time
I2SWS→I2SCK
Hold time
I2SCK↑→I2SDO
Delay time^*1
I2SCK↑→I2SDO
Delay time^*2
I2SDI→I2SCK↓
Setup time
I2SDI→I2SCK↓
Hold time
Input signal rise time
Input signal fall time
fSCYC
tSHW
tSLW
tSFI
tHFI
tDDO
tDFB1
tSDI
tHDI
tFI
tFI
I2SCK
I2SCK
I2SCK,
I2SWS
I2SCK,
I2SWS
I2SCK, I2SDO
I2SCK, I2SDI
I2SCK,
I2SWS, I2SDI
1: Except for the first bit of transmission frame
2: When FSPH bit = 1.
Conditions
-
-
-
-
-
-
-
-
-
-
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Min
Max
-
12.288
Unit
MHz
Remarks
45
55
%
45
55
%
8
-
ns
0
-
ns
0
32
ns
0
32
ns
8
-
ns
0
-
ns
-
5
ns
-
5
ns
Notes:
− When the external load capacitance CL = 20 pF
− When I2SWS = 48 kHz, I2MCLK = 256×I2SWS
Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter 7-2: I²S (Inter-IC Sound bus)
Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details.
Document Number: 002-05030 Rev.*A
Page 180 of 207