S6E2C2 Datasheet, PDF (152/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 1)
Parameter
Baud rate
Serial clock cycle time
SCK↓→SOT delay time
SIN→SCK↑ setup time
SCK↑→SIN hold time
SOT→SCK↑ delay time
Serial clock L pulse width
Serial clock H pulse width
SCK↓→SOT delay time
SIN→SCK↑ setup time
SCK↑→SIN hold time
SCK fall time
SCK rise time
Symbol
-
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
tF
tR
Pin
Name
-
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Conditions
-
Internal shift
clock
operation
External shift
clock
operation
VCC < 4.5 V
Min
Max
-
25
4tCYCP
-
- 10
+ 10
14
-
12.5*
5
-
2tCYCP - 10
-
2tCYCP - 5
-
tCYCP + 10
-
-
15
5
-
5
-
-
5
-
5
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Min
Max
-
25
4tCYCP
-
Unit
Mbps
ns
- 10
+ 10 ns
12.5
-
ns
5
-
ns
2tCYCP - 10
-
ns
2tCYCP - 5
-
ns
tCYCP + 10
-
ns
-
15
ns
5
-
ns
5
-
ns
-
5
ns
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the following pins:
No chip select: SIN4_0, SOT4_0, SCK4_0
Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0
− When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)
Document Number: 002-05030 Rev.*A
Page 152 of 207