S6E2C2 Datasheet, PDF (115/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
12.4.4 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Min
Value
Typ
Max
Unit
PLL oscillation stabilization wait time*¹
(lock up time)
tLOCK
100
-
-
μs
PLL input clock frequency
fPLLI
4
-
16
MHz
PLL multiplication rate
-
13
-
100 multiplier
PLL macro oscillation clock frequency
fPLLO
200
-
400
MHz
Main PLL clock frequency*²
fCLKPLL
-
-
200
MHz
Remarks
*1: Time from when the PLL starts operating until the oscillation stabilizes
*2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual
Main Part (002-04856).
12.4.5 Operating Conditions of USB/Ethernet PLL・I²S PLL (in the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
PLL oscillation stabilization wait time^*1
(lock up time)
PLL input clock frequency
PLL multiplication rate
PLL macro oscillation clock frequency
USB/Ethernet clock frequency ^*2
I²S clock frequency ^*3
Symbol
Min
Value
Typ
Max
Unit
Remarks
tLOCK
100
-
-
μs
fPLLI
-
fPLLO
fCLKPLL
fCLKPLL
4
13
200
-
-
-
16
MHz
-
100 multiplier
-
400
MHz USB/Ethernet
384
MHz
I²S
-
50
MHz
After the M
frequency division
-
12.288
MHz
After the M
frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes
*2: For more information about USB/Ethernet clock, see CHAPTER 2-2: USB/Ethernet Clock Generation in FM4 Family
Peripheral Manual Communication Macro Part (002-04862).
*3: For more information about I²S clock, see Chapter 7-1: I²S Clock Generation in FM4 Family Peripheral Manual
Communication Macro Part (002-04862).
Document Number: 002-05030 Rev.*A
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