S6E2C2 Datasheet, PDF (169/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
12.4.16 SD Card Interface Timing
Default-Speed Mode
Clock CLK (All values are referenced to VIH and VIL transition points)
(VCC = 2.7V to 3.6V, VSS = 0V)
Parameter
Clock frequency Data
Transfer Mode
Symbol
fPP
Pin Name
S_CLK
Conditions
Value
Min
Max
0
25
Remarks
MHz
Clock frequency
Identification Mode
Clock low time
Clock high time
Clock rise time
Clock fall time
fOD
S_CLK
CCARD ≤ 10
0/100
400
kHz
pF
tWL
S_CLK
(1card)
10
tWH
S_CLK
10
-
ns
-
ns
tTLH
S_CLK
-
10
ns
tTHL
S_CLK
-
10
ns
* 0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
Card Inputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol Pin Name
Input set-up time
Input hold time
tISU
S_CMD,
S_DATA3: 0
tIH
S_CMD,
S_DATA3: 0
Conditions
CCARD ≤ 10 pF
(1card)
Value
Min
Max
5
-
5
-
Remarks
ns
ns
Card Outputs CMD, DAT (referenced to Clock CLK)
Parameter
Symbol Pin Name
Output Delay time during
Data Transfer Mode
Output Delay time during
Identification Mode
tODLY
tODLY
S_CMD,
S_DATA3: 0
S_CMD,
S_DATA3: 0
Conditions
CCARD ≤ 40 pF
(1card)
Value
Min
Max
0
14
0
50
Remarks
ns
ns
S_CLK
VIH
(SD Clock)
tTHL
S_CMD,
S_DATA3: 0
(Card Input)
S_CMD,
S_DATA3: 0
(Card Output)
VIL
tODLY(Max)
tWL
VIL
tISU
VIH
VIL
tWH
VIH
tTLH
tIH
VIH
VIL
VOH
VOL
Default-Speed Mode
VIH
tODLY(Min)
VOH
VOL
Notes:
− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is
the Host.
− For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual
Main Part (002-04856).
Document Number: 002-05030 Rev.*A
Page 169 of 207