S6E2C2 Datasheet, PDF (168/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
Fast Mode Plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCL clock frequency
(Repeated) Start condition
hold time
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
SCL clock frequency
(Repeated) Start condition
hold time
SDA ↓ → SCL ↓
Data setup time
SDA ↓ ↑ → SCL ↑
Stop condition setup time
SCL ↑ → SDA ↑
Bus free time between
Stop condition and
Start condition
Noise filter
Symbol
fSCL
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUF
tSP
Conditions
CL = 30 pF,
R = (Vp/IOL)^*1
60 MHz ≤
tCYCP＜80 MHz
80 MHz ≤
tCYCP ≤100 MHz
Fast Mode Plus (Fm+)*6
Min
Max
0
1000
0.26
-
0.5
0.26
0.26
0
-
-
-
0.45^{*2, *3}
50
-
0.26
-
0.5
-
6 tCYCP^*4
-
8 tCYCP^*4
-
Unit Remarks
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
*5
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal.
*3: The Fast mode I²C bus device can be used on a Standard-mode I²C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns.”
*4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I²C is connected,
see "8.Block Diagram" in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the
APB bus clock frequency.
*6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I²C Fm+ in the EPFR register.
See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details.
Document Number: 002-05030 Rev.*A
Page 168 of 207