S6E2C2 Datasheet, PDF (167/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
12.4.15 I²C Timing
Standard-mode, Fast-mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
Stop condition setup time
SCL ↑ → SDA ↑
Bus free time between
"Stop condition" and
"START condition"
Noise filter
Symbol
fSCL
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
Conditions
CL = 30 pF,
R = (Vp/IOL)^*1
Standard-mode
Min
Max
0
100
4.0
-
4.7
-
4.0
-
4.7
-
0
3.45^*2
250
-
4.0
-
tBUF
4.7
-
2 MHz ≤
tCYCP＜40 MHz
2 tCYCP^*4
-
tSP
40 MHz ≤
tCYCP ＜60 MHz
60 MHz ≤
tCYCP ＜80 MHz
4 tCYCP^*4
6 tCYCP^*4
-
-
80 MHz ≤
tCYCP ≤100 MHz
8 tCYCP^*4
-
Fast-mode
Min
Max
0
400
0.6
-
1.3
-
0.6
-
0.6
-
Unit Remarks
kHz
μs
μs
μs
μs
0
0.9^*3
μs
100
-
ns
0.6
-
μs
1.3
2 tCYCP^*4
4 tCYCP^*4
6 tCYCP^*4
8 tCYCP^*4
-
μs
-
ns
-
ns
*5
-
ns
-
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal.
*3: Fast-mode I²C bus device can be used on a Standard-mode I²C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns.”
*4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I²C is connected,
see "8.Block Diagram" in this data sheet.
When using Standard-mode, the peripheral bus clock must be set more than 2 MHz.
When using Fast-mode, the peripheral bus clock must be set more than 8 MHz.
*5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the
APB bus clock frequency.
Document Number: 002-05030 Rev.*A
Page 167 of 207