S6E2C2 Datasheet, PDF (134/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
Synchronous Serial (SPI = 1, SCINV = 0)
Parameter
Baud rate
Serial clock cycle time
SCK↑→SOT delay time
SIN→SCK↓
setup time
SCK↓→SIN hold time
SOT→SCK↓ delay time
Serial clock L pulse width
Serial clock H pulse width
SCK↑→SOT delay time
SIN→SCK↓
setup time
SCK↓→SIN hold time
SCK fall time
SCK rise time
Symbol
-
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSOVLI
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
tF
tR
Pin
Name
-
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Conditions
-
Internal shift
clock
operation
External shift
clock
operation
VCC < 4.5 V
Min
Max
-
8
4tCYCP
-
- 30
+ 30
50
-
0
-
2tCYCP -
30
-
2tCYCP -
10
-
tCYCP +
10
-
-
50
10
-
20
-
-
5
-
5
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Min
Max
-
8
4tCYCP
-
Unit
Mbps
ns
- 20
+ 20
ns
30
-
ns
0
-
ns
2tCYCP -
30
-
ns
2tCYCP -
10
-
ns
tCYCP +
10
-
ns
-
30
ns
10
-
ns
20
-
ns
-
5
ns
-
5
ns
Notes:
− The above characteristics apply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function
serial is connected, see 8. Block Diagram in this data sheet.
− These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and
SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-05030 Rev.*A
Page 134 of 207