S6E2C2 Datasheet, PDF (178/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
12.4.20 I²S Timing
Master Mode Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Output frequency
Output clock pulse width
I2SCK→I2SWS
delay time
I2SCK→I2SDO
delay time*
I2SDI→I2SCK
setup time
I2SDI→I2SCK
hold time
Input signal rise time
Input signal fall time
Symbol
fMCYC
tMHW
tMLW
tDFS
tDDO
tHSDI
tHDI
tFI
tFI
Pin Name
I2SCK
I2SCK
I2SCK,
I2SWS
I2SCK,
I2SDO
I2SCK,
I2SDI
I2SDI
Conditions
-
-
-
-
-
-
-
-
Value
Min
Max
-
12.288
45
55
45
55
0
24.0
0
24.0
25.0
-
0
-
-
5
-
5
Unit
MHz
%
%
ns
ns
ns
ns
ns
ns
Remarks
*: Except for the first bit of transmission frame
Note:
− When the external load capacitance CL = 20 pF
− When I2SWS = 48 kHz, I2MCLK = 256 × I2SWS
Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz.
See CHAPTER 7-2: I²S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part
(002-04862) for the details.
Document Number: 002-05030 Rev.*A
Page 178 of 207