S6E2C2 Datasheet, PDF (119/207 Pages) Cypress Semiconductor – 32-bit ARM® Cortex®-M4F FM4 Microcontroller

S6E2C2 Series
Separate Bus Access Asynchronous SRAM Mode
Parameter
MOEX
Minimum pulse width
MCSX↓→Address
output delay time
MOEX↑→Address
hold time
MCSX↓→
MOEX↓delay time
MOEX↑→
MCSX↑time
MCSX↓→
MDQM↓delay time
Data set up→MOEX↑
time
MOEX↑→
Data hold time
MWEX
Minimum pulse width
MWEX↑→Address
output delay time
MCSX↓→
MWEX↓delay time
MWEX↑→
MCSX↑delay time
MCSX↓→
MDQM↓delay time
MCSX↓→
Data output time
MWEX↑→
Data hold time
Symbol
Pin Name Conditions
tOEW
MOEX
-
tCSL – AV
MCSX[7: 0],
MAD[24: 0]
-
tOEH - AX
MOEX,
MAD[24: 0]
-
tCSL - OEL
-
MOEX,
MCSX[7: 0]
tOEH - CSH
-
tCSL - RDQML
MCSX,
MDQM[3: 0]
-
tDS - OE
MOEX,
MADATA[31: 0]
-
tDH - OE
MOEX,
MADATA[31: 0]
-
tWEW
MWEX
-
tWEH - AX
MWEX,
MAD[24: 0]
-
tCSL - WEL
-
MWEX,
MCSX[7: 0]
tWEH - CSH
-
tCSL-WDQML
MCSX,
MDQM[3: 0]
-
tCSL-DX
MCSX,
MADATA[31: 0]
-
tWEH - DX
MWEX,
MADATA[31: 0]
-
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Min
Max
Unit Remarks
MCLK×n-3
-
ns
-9
+9
ns
0
MCLK×m+9 ns
MCLK×m-9 MCLK×m+9 ns
0
MCLK×m+9 ns
MCLK×m-9 MCLK×m+9 ns
20
-
ns
0
-
ns
MCLK×n-3
-
ns
0
MCLK×m+9 ns
MCLK×n-9 MCLK×n+9 ns
0
MCLK×m+9 ns
MCLK×n-9 MCLK×n+9 ns
MCLK-9
MCLK+9
ns
0
MCLK×m+9 ns
Note:
− When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)
Document Number: 002-05030 Rev.*A
Page 119 of 207