AMIS-53000 Datasheet, PDF (80/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
Data Sheet
7.1.6. Start of Frame
The start of frame byte is transmitted when this register is non-zero. It’s used as an aid for the receiver clock and data recovery circuit
in modes where the fast phase alignment feature is enabled.
Table 90: Start of Frame - 0X19 [25]
Bit Name
Comment
7:0 _{SOF [7:0]}
8-bit code sent prior to chip ID in TX and Burst
7.1.7. Data Rate 1
The data rate 1 and data rate 0 registers are used to set user defined data rates. These registers are loaded from ROM when a
discrete data rate is selected. The following equation is used to calculate the value for CUST_DR:
where DataRate is the desired data rate, and F_{sample_clock} is the frequency selected for the sample clock. This register is loaded with the
discrete rate if selected.
Table 91: Data Rate1 - 0X29 [41]
Bit Name
Comment
7:0 _{CUST_DR [15:8]} Upper byte of user defined data rate/discrete data rate
7.1.8. Data Rate 0
Table 92: Data Rate0 - 0X2A [42]
Bit Name
Comment
7:0 _{CUST_DR [7:0]} Lower byte of user defined data rate/discrete data rate
7.1.9. CRC Polynomial
This register allows a designer to change the CRC Polynomial used in the AMIS-53000. The register represents the presence of the
powers in the CRC equation. For example:
The Polynomial x8+x5+x2+x+1 is encoded by assuming the polynomial will always have a high order bit.
So the binary representation is: 1 0010 0111
This is set as the value 0X27 (HEX) in the register
(See “Koopman, P. & Chakravarty, T., “ Ccylic Redundancy Code (CRC) Polynomial Selection For Embedded Networks” DSN04, June
2004.” for more information.)
Table 93: CRC Poly - 0X30 [48]
Bit Name
Comment
7:0 _{CRC_POLY [7:0]}
CRC polynomial value
AMI Semiconductor – Aug. 05, Rev. 1.0
80
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