AMIS-53000 Datasheet, PDF (55/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
Data Sheet
Over-Sampling Clock (Ts Clock): All three detectors use the Ts clock as the sampling clock for the transition from analog to
digital. This clock should be set to the highest rate possible, but not greater than 400x the data rate, to ensure adequate
phase information. For the discrete data rates, this value is pre-programmed for those rates.
Data Rate Clamp: The data rate clamp restricts the clock recovery circuit from wandering when an actual signal is not
present, and the phase error signals being generated come only from noise. Small fractional values for the clamp can lead to
longer lock times since the clock recovery PLL may not be able to make as large of a correction as is necessary all at once.
Channel Clamp: This clamping circuit is used to hold the low data rate FSK PLL detector within the specified limits to prevent
the PLL from wandering in the absence of signal.
CDR Operation
This circuit utilizes an all digital PLL (ADPLL) to recover the clock from the raw sliced data. The slicer output is integrated over a bit
time to provide a phase error, and the sign of the integration is used to determine the data symbol.
When using the AMIS-53000 in AM mode with any of the packet framing options enabled, it is necessary to have the SOF byte for
proper start-up of the AM CDR circuit. It is recommended that the CDR is set up with the activity check, and fast phase alignment
features enabled for the packet framing modes. The preamble that the AMIS-53000 will transmit in AM mode is CW, hence the SOF
byte is used by the fast phase alignment feature in the CDR to acquire lock. The suggested SOF for AM NRZ format is #55h. This will
provide the most transitions for the clock recovery circuit to acquire lock prior to the incoming packet. For Manchester operation, the
suggested SOF is #0A. This will provide early transitions for phase lock, and 4 bits to align the Manchester decode.
Because there are no transitions during the preamble in AM mode, the CDR relies on the fast phase alignment for acquiring lock. As
this is the case, the length of the preamble can be quite short as long as the activity check is enabled. The preamble should be long
enough to trip the activity detection circuitry such that the fast phase alignment circuit is reset at the beginning of the SOF. This
guarantees that the fast phase alignment will kick in during the SOF. The suggested length for the preamble is 4 BT’s for Manchester
with activity check set to 4 BT’s, and 10 or 20 for NRZ, with activity check set to 8 or 16 respectively. Note in the NRZ case, enabling
activity check will require the data be formatted to guarantee at least one transition in the data during the length of activity check (i.e.
every 8 or 16 BT’s).
Setup registers descriptions:
ID Dwell- Set a time that the CDR circuit will continue to search for the chip ID.
CDR Config- Set the parameters for the clock and data recovery circuits.
Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate. (See
Section 7.1.3)
Start of Frame- Byte used to tell the AMIS-53000 receiver that data will start. (See Section 7.1.6)
Clock Recovery Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed. For
user defined data rates, this value needs to be calculated.
Chip ID Dwell Timer
Used to specify how long the clock and data recovery circuit will stay active after energy has been detected, looking for a valid chip ID.
The part will look for either the chip ID or the global ID.
Table 40: Chip ID Dwell Timer - 0X14 [20]
Bit Name
Comment
7:0 _{C_DWELL [7:0]}
00h: Code dwell timer disabled (for standard receive wake on code)
01h – FFh: Code dwell time = C_DWELL*bit time * 8
AMI Semiconductor – Aug. 05, Rev. 1.0
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