AMIS-53000 Datasheet, PDF (34/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
6.1.4.3. Sequential Register Write
Data Sheet
Figure 28: Sequential Control Data Read/Write with the I²C Interface
When setting the AMIS-53000 up for an application it sometimes is nice to write data to a number of registers one after the other. The
write control byte, register address and first data byte are transmitted to the AMIS-53000 in the same way as in a byte write. However,
instead of generating a stop condition, the master can continue to write register locations. Upon receipt of each word, the address is
internally incremented by ‘1’. If the master should transmit more words than the AMIS-53000 has address locations, the address will roll
over.
It is a similar approach to read a register value. The write control byte and register address are transmitted to the AMIS-53000 in the
same way as in a byte write. After receiving another acknowledge signal from the AMIS-53000, the master device will immediately
follow with another start sequence, however, the R/W bit is now set high telling the slave device that the master wants the contents of
the register (addressed with the write command) to be placed on the SDA bus line. After the 8 bits are read by the master, the master
acknowledges the reception. The AMIS-53000 will increment the register address and continue to output register values. After the last
register value is received by the master, the master does not respond with an acknowledge but sends the stop sequence.
6.1.4.4. Current Address Read
The internal address counter maintains the last address addressed, incremented by ‘1’. If the last instruction received was to access
register N, the current address read operation will read the contents from register N+1. The timing for the current address read is to
send a start bit followed by the 7-bit device address, with the R/W bit set to one. The slave will acknowledge, after which the 8-bit
register contents will be transmitted. The master does not acknowledge the transmission, but does generate a stop bit.
AMI Semiconductor – Aug. 05, Rev. 1.0
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