AMIS-53000 Datasheet, PDF (79/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
Data Sheet
Table 88: General OptionsA - 0X0C [12]
Bit
Name
State
1
7
Use ID in RX and TX
0
6
Length of Packet
Enable
1
0
1
5
CRC Enable
0
4
Temperature
Compensation
1
0
1
3
Pull up Disable
0
00
[2:1] POR State
01
10
11
1
0
Standby Mode
0
Comment
Wake on ID in RX, send ID in TX
Enables the part to frame packets
Enables CRC (packet length must be enabled)
RF center frequency temperature compensation enabled
Temperature compensation is disabled
Pull ups on IIC clock and data and SSN pins disabled
Standby
Idle
RX
TX
Crystal only mode, system clock output active
Low-power standby mode
7.1.5. General Options B
General options B contains more option bits for the general setup and operation of the AMIS-53000.
System Clock Output Frequency: Sets the frequency of the output clock on the SYSclk pin when enabled.
RXTX Sampling Edge: Specifies which edge of DCLK should be used to sample the RXTX pin.
Auto Increment Disable: When enabled, a multiple address read or write command on the register interface will read/write
only the address given in the command multiple times.
Data Interface Clock Frequency: Sets the clock frequency for the data interface when the AMIS-53000 is configured to be
the master of the data interface. For modes in which the AMIS-53000 does not buffer the packet, the interface speed will
always be the data rate, regardless of this setting.
Data Interface Slave/Master: Specifies whether the AMIS-53000 is the master or slave for the data interface.
4-Wire Data Interface: Enables the 4-wire SPI data interface. When low, RXTX is bi-directional.
Table 89: General OptionsB - 0X0D [13]
Bit Name
7
4-Wire Data Interface
6
Data Interface Slave/Master
5,4 _{Data Interface Clock Frequency}
3
NU
2
RXTX Sampling Edge
1,0 System Clock Output
Frequency
State
1
0
1
0
11
10
01
00
1
0
11
10
01
00
Comment
Enabled
AMIS-53000 is slave
AMIS-53000 is master, clock speed determined by bits 5, 4
1MHz
500kHz
100kHz
Baud clock
Data bits are sampled on the rising edge of DCLK on the interface
Data bits are sampled on the falling edge of DCLK on the interface
12MHz (24MHz external crystal)
6MHz (24MHz external crystal)
3MHz (24MHz external crystal)
Off
AMI Semiconductor – Aug. 05, Rev. 1.0
79
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