AMIS-53000 Datasheet, PDF (30/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
Data Sheet
External controller can read registers
External controller can issue a immediate transmit via the xBURST input
External controller can receive an interrupt (xINT) from the AMIS-53000
Setup registers descriptions:
I²C/3-wire select- First write to the interface sets the type of interface until AMIS-53000 is power cycled.
6.1.2. Serial Control Interface: Configuration
The AMIS-53000 can automatically detect the type of interface for the serial control bus. The interface pins are then given the
definitions as shown in Table 14. The detection depends on the status of the AMIS-53000 pins as shown in Figure 23.
Table 14: Control Port Pin Definitions
Pin Name
I²C Mode
3-Wire Mode
SCLK
SCL
SCLK
SDATA
SDA
R/W controlled
SSN
Internal pull up
SSN
Figure 23: Control Interface Selection
Simply addressing the part with the desired protocol performs initial interface selection. After the first communication with the part, the
selection is locked until power is removed from the device. The internal logic for determining which protocol to use on initial power up is
as follows:
I²C: If SSN is high and an I²C start bit is detected, I²C mode is enabled.
3-wire: If SSN is low, and a negative edge on SCLK detected, 3-wire mode is enabled.
The internal pull ups on SCLK and SDATA can also be disabled for I²C applications using external pull ups.
Table 15: Control Interface Pull Up Control
Mode
SCLK, SDATA Pull Ups
I²C
Controlled by bit 3 of the general
options A register
3-wire
Controlled by bit 3 of the general
options A register
SSN Pin Configuration
Not used (internal pull up)
SSN: normal mode
AMI Semiconductor – Aug. 05, Rev. 1.0
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