AMIS-53000 Datasheet, PDF (28/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
Data Sheet
6.0 User’s Guide
This user’s guide divides the control register description of the AMIS-53000 into functional areas; command register flow diagrams,
frequency generation, receiver, transmitter, idle, data/control interfaces, Burst transmit, and MICS features.
6.1 Control Serial Interface Bus Description
Table 11: Control Interface Physical Configuration
Interface Function
I²C
Control
Clock
Pin
SCLK
Source
Master
Data
Output
SDATA
3-Wire
Control
SCLK Master SDATA
Input
SDATA
SDATA
Select
None
SSN
AMIS-53000
Slave only
Slave only
The AMIS-53000 employs two different control interfaces. Communication with the AMIS-53000 control registers is through either a
3-wire bus or through a 2-wire (with third line for control/status) I²C compatible bus. The state of the control bus is detected by the
AMIS-53000 at the first communication, I²C or 3-wire, and is set in that function (3-wire or I²C) as long as power remains applied to the
part.
3-wire control communication bus
I²C control communication bus
AMIS-53000 is always the slave
6.1.1. Control Interface Protocol
The AMIS-53000 control interface allows an external controller to write instructions to the registers of the AMIS-53000 and control the
functions of the AMIS-53000. The external controller can also read the registers and status of the AMIS-53000. The control interface
can be configured as a slave device in either a 2-wire I²C interface bus or a 3-wire serial interface.
AMI Semiconductor – Aug. 05, Rev. 1.0
www.amis.com
Figure 21: Control I²C Protocol Format
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