AMIS-53000 Datasheet, PDF (54/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
Data Sheet
FM PLL Detector Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed. For
user defined data rates, this value needs to be calculated.
PLL Detector Loop Filter Setting
A program (AMIS-53CALC.exe available from AMIS) has been created to aid in the design of loop filter settings.
Table 39: PLL Detector Loop Filter Setting - 0X2B [43]
Bit Name
Comment
7:0 _{PLL_CO [7:0]}
PLL loop filter setting
FM PLL (Low Data Rate FSK)
The AMIS-53000 uses a PLL function to recover the data from a FM/FSK modulated signal with data rates 20kbps or lower. This circuit
uses an A DPLL for demodulation, the output of which is fed to the AM CDR circuit to recover the clock, and additionally filter the output
data.
The preamble sent by the AMIS-53000 when configured as NRZ FM is a repeating sequence of 1’s and 0’s. This gives the CDR circuit
and PLL demodulator sufficient edges to acquire lock. Hence, for the NRZ case it is unnecessary to include a SOF byte. In
Manchester mode, the preamble is specified as all 1’s (or 0’s). This gives the clock recovery circuit the most edges for lock acquisition.
However, due to the ambiguity of the preamble, a SOF byte is necessary for the Manchester decoding block. The suggested SOF for
this is either #55h or #AAh. The length of preamble necessary for this mode is dependant upon the loop bandwidth for the clock
recovery PLL.
Setup registers descriptions:
Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate. (See
Section 7.1.3)
Peak Deviation- The peak deviation register stores the value to be used for both transmit and receive. In the FFT FM receive
mode, this value is used to set-up the FFT bins. (See Sections 6.4.1.5 and 6.4.1.6)
M PLL Detector Loop Filter- For the discrete data rates, the values for the loop filter coefficients are preprogrammed. For
user defined data rates, this value needs to be calculated. (See PLL Detector Loop Filter Setting)
6.5.1.5. Clock and Data Recovery
The AMIS-53000 device performs clock and data recovery for both AM/OOK/ASK and FM/FSK signals. An internal clock in the
AMIS-53000 is programmed to be nearly the same rate as the expected data rate in the incoming signal. This clock is then
synchronized to the incoming data rate by extracting a clock from the data. This loop recovery method recovers data without much of
the jitter and noise associated with wireless communication links.
Before launching headlong into the operation of the detectors, and how to set them up, it is instructive to review the following related
registers, setup options and their functions.
Setup registers descriptions:
Fast Phase Alignment: In both the AM and PLL based FM modes (lower data rate), the AMIS-53000 can be configured to
quickly acquire phase lock on incoming data. The pattern necessary for the fast phase alignment is simply ‘1010’. This
function can be enabled in the CDR options A register. With this function enabled, the CDR circuit will operate with minimum
power consumption until the ‘1010’ sequence is received. A 32-bit correlation is used to not only recognize the 1010 pattern,
but also to instantaneously provide a phase correction to the clock recovery circuit allowing very fast (less than 4 bit) lock
times locking the incoming data.
Activity Check: This function can be used in conjunction with the fast phase alignment to reset the clock and data recovery
block back into its minimal power consumption mode when no transitions are detected on the data line for a specified period.
The check can be configured for 4, 8 or 16 bit times.
AMI Semiconductor – Aug. 05, Rev. 1.0
54
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